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l4990 l4990a primary controller current-mode control pwm switching frequency up to 1mhz low start-up current < 0.45ma high-current output drive suitable for power mosfet (1a) fully latched pwm logic with dou- ble pulse suppression programmable duty cycle 100% and 50% maximum duty cycle limit programmable soft start primary overcurrent fault detec- tion with re-start delay pwm uvlo with hysteresis in/out synchronization disable latched internal 100ns leading edge blank- ing of current sense package: dip16 and so16w description this primary controller i.c., developed in bcd60ii technology, has been designed to implement off line or dc-dc power supply applications using a fixed frequency current mode control. based on a standard current mode pwm control- ler this device includes some features as pro- grammable soft start, in/out synchronization, disable (to be used for over voltage protection and for power management), precise maximum duty cycle control, 100ns (typ) leading edge blanking on current sense, pulse by pulse current limit and overcurrent protection with soft start in- tervention. july 1999 ? + - + - timing 2 3 + - 14 t vref clk 2.5v + - 1.2v 13 blanking pwm fault soft-start r sq 25v 16v/10v vref ok dis + - e/a 1v r 2r dis 2.5v 7 6 5 11 10 9 4 8 15 1 13v pwm uvlo 12 sgnd comp ss isen dis dc rct sync dc-lim v cc vref d98in1002 vfb pgnd out v c over current block diagram ordering numbers: l4990/l4990a(dip16) L4990D/l4990ad (so16w) multipower bcd technology dip16 so16w 1/24
absolute maximum ratings symbol parameter value unit v cc supply voltage (i cc < 50ma) (*) selflimit v i out output peak pulse current 1.5 a analog inputs & outputs (6,7) -0.3 to 8 v analog inputs & outputs (1,2,3,4,5,15,14 13) -0.3 to 6 v p tot power dissipation @ t amb =70 c1w t j junction temperature, operating range -25 to 125 c t stg storage temperature, operating range -55 to 150 c (*) maximum package power dissipation limits must be observed thermal data symbol parameter value unit r th j-amb thermal resistance junction to ambient dip16 80 c/w r th j-amb thermal resistance junction to ambient so16 120 c/w pin functions n. name function 1 sync synchronization. a synchronization pulse terminates the pwm cycle and discharges ct 2 rct oscillator pin for external c t ,r t components 3 dc duty cycle control 4 vref 5.0v +/-1.5% reference voltage 5 vfb error amplifier inverting input 6 comp error amplifier output 7 ss soft start pin for external capacitor css 8v cc supply for internal osignalo circuitry 9v c supply for power section 10 out high current totem pole output 11 pgnd power ground 12 sgnd signal ground 13 isen current sense 14 dis disable. it must never be left floating. tie to sgnd if not used. 15 dc-lim connecting this pin to vref, dc is limited to 50%. if it is left floating or grounded no limitation is imposed 16 nc not connected sync rct dc vref vfb ss comp 1 3 2 4 5 6 7 out sgnd pgnd isen dis dc-lim n.c. 16 15 14 13 12 10 11 d95in197 v cc 8v c 9 pin connection l4990 - l4990a 2/24
electrical characteristics (v cc = 15v; t j = 0 to 70 c; unless otherwise specified.) symbol parameter test condition min. typ. max. unit reference section v o output voltage t j =25 c; i o = 1ma 4.925 5.0 5.075 v line regulation v cc = 12 to 20v 2.0 15 mv load regulation i o = 1 to 20ma 5.0 20 mv t s temperature stability 0.4 mv/ c total variation line, load, temperature 4.875 5.0 5.125 v i os short circuit current vref = 0v 30 150 ma power down/uvlo v cc = 8.5v; i sink = 0.5ma 0.2 0.5 v oscillator section initial accuracy t j =25 c; r t = 4.42k w ; c t = 1nf; pin 15 vref 285 300 315 khz accuracy r t = 4.42k w ;v cc = 12 to 20v; c t = 1nf; pin 15 = vref 279 300 321 khz initial accuracy t j =25 c; r t = 4.42k w ; c t = 1nf; pin 15 open 280 295 310 khz accuracy r t = 4.42k w ;v cc = 12 to 20v; c t = 1nf; pin 15 open 275 295 315 khz duty cycle pin 3 = 0,7v, pin 15 = vref pin 3 = 0.7v, pin 15 = open 0 0 % % duty cycle r t = 4.42k w c t = 1nf pin 3 = 3.2v, pin 15 = vref pin 3 = 3.2v, pin 15 = open 45 90 % % duty cycle accuracy pin 3 = 2.02v, pin 15 = open 37 40 43 % oscillator ramp peak 3.0 v oscillator ramp valley 1.0 v error amplifier section input bias current v fb to gnd 0.2 1.0 m a v i input voltage v comp =v fb 2.42 2.5 2.58 v g opl open loop gain v comp = 2 to 4v 60 90 db svr supply voltage rejection v cc = 12 to 20v 85 db v ol output low voltage i sink = 2ma, v fb = 2.7v 1.1 v v oh output high voltage i sou rce = 0.5ma, v fb = 2.3v 5 6 v i o output source current v comp > 4v, v fb = 2.3v 0.5 1.3 ma output sink current v comp = 1.1v, v fb = 2.7v 2 6 ma unit gain bandwidth 2 4 mhz s r slew rate 8 v/ m s pwm current sense section i b input bias current i sen =0 3 15 m a i s maximum input signal v comp = 5v 0.92 1.0 1.08 v delay to output 100 ns gain 2.85 3 3.15 v/v soft start i ssc ss charge current 14 20 26 m a i ssd ss discharge current vss = 0.6v 200 m a v sssat ss saturation voltage dc = 0% 0.6 v v ssclamp ss clamp voltage 7 v leading edge blanking internal masking time 100 ns l4990 - l4990a 3/24
functional description the i.c. contains a standard pwm current mode control section with improved performance with respect to the uc384x family. enhanced features include start-up bias current reduced to < 270 m a (typ), improved e/a perform- ance (4mhz b/w, 1.3ma source current, high- slew rate) accurate 1mhz oscillator, and also re- duced propagation delays in the critical path from current sense to output. additional features soft start (ss) an external capacitor is charged by an internal constant current source (20 m a) to generate a ss signal which clamps the e/a output the ss pin doubles as a fault reset delay func- tion as described below. current limit / reset delay an internal high-speed current limit comparator electrical characteristics (continued.) symbol parameter test condition min. typ. max. unit output section v ol output low voltage i o = 250ma 1.0 v v oh output high voltage i o = 20ma; v cc = 12v 10 10.5 v i o = 200ma; v cc = 12v 9 10 v v out clamp output clamp voltage i o = 5ma; v cc = 20v 13 v collector leakage v cc = 20v v c = 24v 100 200 m a fall time c o = 1nf c o = 2.5nf 20 35 60 ns ns rise time c o = 1nf c o = 2.5nf 50 70 100 ns ns uvlo saturation v cc =0vtov ccon ;i sink = 10ma 1.0 v supply section v ccon startup voltage l4990 l4990a 15 7.8 16 8.4 17 9 v v v ccoff minimum operating voltage l4990 l4990a 9 7 10 7.6 11 8.2 v v v hys voltage after turn-on hysteresis l4990 l4990a 5.5 0.5 6 0.8 v v i s start up current before turn-on at: v cc =v ccon - 0.5v 100 270 450 m a i op operating current c t = 1nf, r t = 4.42k w ,c o =1nf 12 18 ma i q quiescent current (after turn on), co =0nf c t = 1nf, r t = 4.42k w , 7.0 10 ma i sh shutdown current 100 270 450 m a v z zener voltage i 8 = 20ma 21 25 30 v synchronization section master operation v 1 clock amplitude i source = 0.8ma 4 v i 1 clock source current vclock = 3.5v 7 ma slave operation v 1 sync pulse low level 1 v high level 3.5 v i 1 sync pulse current vsync = 3.5v 0.8 ma over current protection v t fault threshold voltage 1.1 1.2 1.3 v disable section shutdown threshold 2.4 2.5 2.6 v l4990 - l4990a 4/24
referenced to 1.2v detects primary over-current conditions. on detection of an overcurrent fault the output is immediately shutdown and the fault is also latched. a fault reset delay is imple- mented by discharging the external soft start (ss) timing capacitor before resetting the fault latch and initiating a softstart cycle. in case of a continuous fault condition the ss ca- pacitor is charged to 5v before being discharged again, to ensure that the fault frequency does not exceed the programmed soft start frequency. duty cycle limit a simple connection between the dc-lim and the available vref activates an internal t- flipflop lim- iting the dc to about 50%. if this pin is not con- nected or grounded, the limit of the duty cycle is extended to about 100% duty cycle control duty cycle dc is externally programmed by set- ting a voltage between 1v (0% dc) and 3v (100% dc) at the dc pin. the programmed volt- age is compared with the oscillator c t capacitor charging waveform to determine the maximum on-time in each period. this function gives a fine control of dc. if this pin is floating the maximum duty cycle de- pends on dc-lim status. synchronization a sync pin eases synchronization of the ic to the external world ( e.g. another ic working in parallel or to tv/monitor sync signal). in tv/monitor applications the timing components r t ,c t are set for a frequency lower than the minimum tv sync frequency. when the tv circuit has powered-up it takes over and the system fre- quency is that of the sync. duty cycle is control- lable using the dc function. in parallel operation of several ic's no mas- ter/slave designation is required as the higher fre- quency ic is automatically the master. controllers to be synchronized have their sync pins tied to- gether and each sync pin operates as a bidirec- tional circuit. the first ic to drive its sync pin is the master and it initiates a discharge of the c t timing capacitor of every controller. the sync in- put signal is edge-triggered and sets an internal osync latcho which ensures full discharge of c t . disable function the dis pin performs a logic level latched-shut- down function. when pulled above 2.5v it shuts down the complete ic with a standby current of <270 m a (typ). to reset the ic the v cc pin must be pulled-down below the lower uvlo threshold (10v). leading edge blanking (leb) an leb interval of 100ns has been incorporated into the ic to blank out the current sense signal during the first 100ns from switch turn-on. this provides noise immunity to turn-on spikes and reduces external rc filtering requirements on the current-sense signal. 6 8 20 30 v14 = 0, osc=disabled tj = 25 c 0 4 8 12162024 0 0.2 0.4 0.6 0.8 1 vcc [v] iq [ma] x y figure 1. quiescent current vs. input voltage. (x = 7.6v and y = 8.4v for l4990a) 8 1012141618202224 210 240 270 300 vcc [v] iq [ua] v14 = vref tj = 25 c figure 2. quiescent current vs. input voltage (after disable). l4990 - l4990a 5/24
8 1012141618202224 7.0 7.5 8.0 8.5 9.0 vcc [v] iq [ma] v14 = 0, v5 = vref rt = 4.5kohm,tj = 25 c 500khz 300khz 1m hz 100khz figure 3. quiescent current vs. input voltage. -50 -25 0 25 50 75 100 125 150 4.9 4.95 5 5.05 5.1 tj ( c) vref [v]) vcc = 15v iref = 1ma figure 7. vref vs. junction temperature. -50 -25 0 25 50 75 100 125 150 4.9 4.95 5 5.05 5.1 tj ( c) vref [v] vcc = 15v iref= 20ma figure 8. vref vs. junction temperature. 8 10121416182022 0 6 12 18 24 30 36 vcc [v] iq [ma] co = 1nf, tj = 25 c dc = 100% 1m h z 50 0kh z 300khz 10 0kh z f igure 5. quiescent current vs. input voltage and switching frequency. 0 5 10 15 20 25 4.9 4.95 5 5.05 5.1 iref [ma] vref [v] vcc=15v tj = 25 c figure 6. reference voltage vs. load current. 8 10121416182022 0 6 12 18 24 30 36 vcc [v] iq [ma] co = 1nf, tj = 25 c dc = 0% 1mhz 500khz 300khz 100khz f igure 4. quiescent current vs. input voltage and switching frequency. l4990 - l4990a 6/24
-50 -25 0 25 50 75 100 125 150 280 290 300 310 320 tj ( c) fsw (khz) rt= 4.5kohm, ct = 1nf vcc = 15v, v15=vref figure 14. switching frequency vs. temperature. 10 0 0.2 0.4 0.6 0.8 1 1.2 6 8 10 12 14 16 isource [a] v sat = v [v] vcc = 15v tj = 25 c figure 10. output saturation. 0 0.2 0.4 0.6 0.8 1 1.2 0 0.5 1 1.5 2 2.5 is ink [a] 10 vsat = v [v ] vcc = 15v tj = 25 c figure 11. output saturation. 1 10 100 1000 10000 0 40 80 120 fsw (hz) svrr (db) vcc=15v vp-p=1v figure 9. vref svrr vs. switching frequency. 10 20 30 40 10 20 50 100 200 500 1000 2000 5000 rt ( kohm) fsw(khz) 100pf 2 20pf 4 70pf 1nf 2.2nf 5.6nf tj = 25 c vcc = 15v ,v15=0v figure 13. timing resistorvs.switching frequency. 0 200 400 600 800 1,000 1,200 1,400 0 10 20 30 40 50 vpin10 [mv] ipin10 [ma] vcc < vccon before turn-on figure 12. uvlo saturation l4990 - l4990a 7/24
0.01 0.1 1 10 100 1000 10000 100000 0 50 100 150 20 40 60 80 100 120 140 f(khz) g [db] phase figure 19. e/a frequency response. 0 102030405060708090100 1 1.5 2 2.5 3 3.5 duty cycle [%] dc control voltage vpin3 [v] rt = 4.5kohm , ct = 1nf v15 = 0v v15 = vref figure 17. maximum duty cycle vs vpin3. -50 -25 0 25 50 75 100 125 150 60 70 80 90 100 110 120 130 tj ( c) delay to output (ns) pin10 = open 1v pulse on pin13 figure18.delayto outputvs junctiontemperature. -50 -25 0 25 50 75 100 125 150 280 290 300 310 320 tj ( c) fsw (khz) rt= 4.5kohm, ct = 1nf vcc = 15v, v15= 0 figure 15. switching frequency vs. temperature. 246810 300 600 900 1,200 1,500 timing capacitor ct [nf] dead time [ns] rt =4.5kohm v15 = 0v v15 = vref figure 16. dead time vs ct. l4990 - l4990a 8/24
application information detailed pin functions description pin 1. sync (in/out synchronization). this func- tion allows the ic's oscillator either to synchronize other controllers (master) or to be synchronized to an external frequency (slave). as a master, the pin delivers positive pulses dur- ing the ramp-down of the oscillator (see pin 2). in slave operation the circuit is edge triggered. refer to fig. 21 to see how it works. when several ic work in parallel no master-slave designation is needed because the fastest one becomes auto- matically the master. during the ramp-up of the oscillator the pin is pulled low by a 600 m a generator. during the ramp-down, that is when the pulse is released, the 600 m a pull-down is disconnected. the pin be- comes a generator whose source capability is typically 7ma (with a voltage still higher than 3.5v). in fig. 20, some practical examples of synchroniz- ing the l4990 are given. l4990 l4990 r t vref sync sync rct rct l4981a (master) l4990 (slave) r t vref sync rct r osc c osc c t l4990 (master) l4981a (slave) sync r osc c t c osc sync (a) (b) (c) r t d97in494a c t vref 4 1 2 1 2 16 18 17 4 2 1 rct 1 2 4 16 17 18 figure 20. synchronizing the l4990. pin 2. rct (oscillator). a resistor (r t ) and a ca- pacitor (c t ), connected as shown in fig. 21 set the operating frequency f osc of the oscillator. c t is charged through r t until its voltage reaches 3v, then is quickly internally discharged. as the voltage has dropped to 1v it starts being charged again + - r2 r3 r1 clamp d1 50 w r t c t d r q 600 m a d97in500b v ref rct sync clk 2 4 1 figure 21. oscillator and synchronization internal schematic. l4990 - l4990a 9/24
the frequency can be established with the aid of fig. 13 diagrams or considering the approximate relationship: f osc @ 1 c t ? ( 0.693 ? r t + k t ) ( 1 ) where k t is defined as: k t = ? ? ? 90, v 15 = vref 160 v 15 = gnd/open ( 2 ) and is linked to the duration of the falling edge of the sawtooth: t d @ 30 ? 10 -9 +k t ? c t (3) t d is also the duration of the sync pulses deliv- ered at pin 1 and defines the upper extreme of the duty cycle range, d x (see pin 15 for d x defini- tion and calculation). in case v 15 is connected to vref, however, the switching frequency of the system will be as high as half f osc . if the ic is to be synchronized to an external oscil- lator, r t and c t should be selected for a f osc lower than the master frequency in any condition (typically, 10-20% ), depending on the tolerance of r t and c t itself. pin 3. dc (duty cycle control). by biasing this pin with a voltage between 1 and 3 v it is possible to set the maximum duty cycle between 0 and the upper extreme d x (see pin 15). if d max is the desired maximum duty cycle, the voltage v3 to be applied to pin 3 is: v 3 =5-2 (2-dmax) (4) d max is determined by internal comparison be- tween v3 and the oscillator ramp (see fig. 22), thus in case the device is synchronized to an ex- ternal frequency f ext (and therefore the oscillator amplitude is reduced), (4) changes into: v 3 = 5 - 4 ? exp ? ? ? - d max r t ? c t ? f ext ? ? ? (5) a voltage below 1v will inhibit the driver output stage. this could be used for a not-latched device disable, for example in case of overvoltage pro- tection (see application ideas). if no limitation on the maximum duty cycle is re- quired (i.e. d max =d x ), the pin has to be left float- ing. an internal pull-up holds the voltage above 3v. should the pin pick up noise (e.g. during esd tests), it can be connected to v ref through a 4.7k w resistor. pin 4. vref (reference voltage). an internal generator furnishes an accurate voltage reference (5v 1.5%) that can be used to supply an external circuit (consider some ten ma). a small film capacitor (1 m f typ.), connected be- tween this pin and sgnd, is recommended to preventswitching noise from affecting the reference. before device turn-on, this pin has a sink current ca- pability of 0.5ma. pin 5. vfb (error amplifier inverting input). the feedback signal is applied to this pin and is com- pared to the e/a internal reference (2.5v). the e/a output generates the control voltage which fixes the duty cycle. the e/a features high gain-bandwidth product, which allows to broaden the bandwidth of the overall control loop, high slew-rate and current capability, which improves its large signal behav- ior. usually the compensation network, which sta- bilizes the overall control loop, is connected be- tween this pin and comp (pin 6). pin 6. comp (error amplifier output). usually, this pin is used for frequency compensation and the relevant network is connected between this pin and vfb (pin 5). compensation networks to- wards ground are not possible since the l4990 e/a is a voltage mode amplifier (low output im- pedance). see application ideas for some exam- ple of compensation techniques. pin 7. ss (soft-start). at device start-up, a ca- pacitor (css) connected between this pin and sgnd (pin 12) is charged by an internal current generator, issc, up to about 7v. during this ramp, the e/a output is clamped by the voltage across css itself and allowed to rise linearly, start- ing from zero, up to the steady-state value im- posed by the control loop. the maximum time in- terval during which the e/a is clamped, referred to as soft-start time, is approximately: + - r2 r1 r t c t d97in501a v ref rct dc to pwm logic 4 3 2 figure 22. duty cycle control. l4990 - l4990a 10/24
t ss @ 3 ? r sense ? i qpk i ssc ? c ss (6) where r sense is the current sense resistor (see pin 13) and i qpk is the switch peak current (flowing through r sense ), which depends on the output load. usually, c ss is selected for a t ss in the or- der of milliseconds. as mentioned before, the soft-start intervenes also in case of severe overload or short circuit on the output. referring to fig. 23, pulse-by-pulse current limitation is somehow effective as long as the on-time of the power switch can be reduced (from a to b). after the minimum on-time is reached (from b onwards) the current is out of control. to prevent this risk, a comparator trips an over- current handling procedure, named 'hiccup' mode operation, when a voltage above 1.2v (point c) is detected on current sense input (isen, pin 13). basically, the ic is turned off and then soft-started as long as the fault condition is detected. as a re- sult, the operating point is moved abruptly to d, creating a foldback effect. fig. 24 illustrates the operation. the oscillation frequency appearing on the soft- start capacitor in case of permanent fault, referred to as 'hiccupo period, is approximately given by: t hic @ 4.5 ? ? ? ? 1 i ssc + 1 i ssd ? ? ? ? c ss ( 7 ) since the system tries restarting each hiccup cy- cle, there is not any latchoff risk. v out t on d.c.m. c.c.m. d a b c i qpk t on(min) 1-2 i qpk i qpk(max) i out i short i out(max) d97in495 figure 23. regulation characteristic and re- lated quantities 7v t hic time short i out i sen fault ss 5v 0.5v d97in496 figure 24. hiccup mode operation. l4990 - l4990a 11/24
ohiccupo keeps the system in control in case of short circuits but does not eliminate power com- ponents overstress during pulse-by-pulse limita- tion (from a to c). other external protection cir- cuits are needed if a better control of overloads is required. pin 8. vcc (controller supply). this pin supplies the signal part of the ic. the device is enabled as vcc voltage exceeds the start threshold and works as long as the voltage is above the uvlo threshold. otherwise the device is shut down and the current consumption is extremely low. an internal zener limits the voltage on vcc to 25v. below this value the ic current consumption is low but increases considerably if this limit is ex- ceeded. a small film capacitor between this pin and sgnd (pin 12), placed as close as possible to the ic, is recommended to filter high frequency noise. pin 9. vc (supply of the power stage). it sup- plies the driver of the external switch and there- fore absorbs a pulsed current. thus it is recom- mended to place a buffer capacitor (towards pgnd, pin 11, as close as possible to the ic) able to sustain these current pulses and in order to avoid them inducing disturbances. this pin can be connected to the buffer capacitor directly or through a resistor, as shown in fig. 25, to control separately the turn-on and turn-off speed of the external switch, typically a power- mos. at turn-on the gate resistance is r g +r g' and turn-off is r g only. pin 10. out (driver output). this pin is the out- put of the driver stage of the external power switch. usually, this will be a powermos, al- though the driver is powerful enough to drive bjt's (1.6a source, 2a sink, peak). the driver is made up of a totem pole with a high- side npn darlington and a low-side vdmos, and delivers a voltage internally clamped, as shown in fig. 25. thus it is possible to supply the driver (pin 9) with higher voltages without any problem of damage for the gate oxide of the external mos, but, of course, the power dissipation on the ic will increase. in uvlo conditions an internal circuit (shown in fig.26) holds the pin low in order to ensure that the external mos cannot be turned on acciden- tally. the peculiarity of this circuit is its ability to mantain the same sink capability (typically, 20ma @ 1v) from v cc = 0v up to the start-up threshold. when the threshold is exceeded and the l4990 starts operating, v refok is pulled high (refer to fig. 26) and the circuit is disabled. it is then possible to omit the obleedero resistor (connected between the gate and the source of the mos) ordinarily used to prevent undesired switching-on of the external mos because of some leakage current. pin 11. pgnd (power ground). the current loop during the discharge of the gate of the external mos is closed through this pin. this loop should be as short as possible to reduce emi and run separately from signal currents return. pin 12 . sgnd (signal ground). this ground ref- erences the control circuitry of the ic, so all the ground connections of the external parts related to control functions must lead to this pin. in laying out the pcb, care must be taken in preventing switched high currents from flowing through the sgnd path. pin 13. isen (current sense). this pin is to be connected to the ohoto lead of the current sense resistor r sense (being the other one grounded), to get a voltage ramp which is an image of the cur- rent of the switch, (i q ). when this voltage is equal to: out rg drive & control 13v v c v cc rg' pgnd rg(on)=rg+rg' rg(off)=rg d97in497a l4990 9 10 11 8 17 13 (v) figure25.turn-on and turn-offspeeds adjustment 10 12 sgnd out v refok d97in538 figure 26. pull-down of the output in uvlo. l4990 - l4990a 12/24
v 13pk = i qpk ? r sense = ( v comp - 1.4 ) 3 ( 8 ) the conduction of the switch is terminated. to increase the noise immunity, a oleading edge blankingo of about 100ns is internally realized as shown in fig. 27. because of that, the smoothing rc filter between this pin and r sense could be re- moved or, at least, considerably reduced. + - i d97in503 isen 0 3v clk 2v + - + - 1.2v from e/a overcurrent comparator pwm comparator to pwm logic to fault logic 13 figure 27. internal leb pin 14. dis (device disable). when the voltage on pin 14 rises above 2.5v the ic is shut down and it is necessary to pull vcc (ic supply volt- age, pin 8) below the uvlo threshold to allow the device to restart. when disabled, the current con- sumption of the ic is as low as before start-up. the pin can be driven by an external logic signal in case of power management, as shown in fig. 28. it is also possible to realize an overvoltage protection, as shown in the section o application ideaso. if used, bypass this pin to ground with a filter ca- pacitor to avoid spurious activation due to noise spikes. if not, it is advisable to connect the pin to sgnd, even though it might be left floating. pin 15. dc-lim (maximum duty cycle limit). the upper extreme, dx, of the duty cycle range de- pends on the voltage applied to this pin. approxi- mately, d x @ r t r t + 230 ( 9 ) if dc-lim is grounded or left floating. instead, connecting dc-lim to vref (half duty cycle op- tion), dx will be set approximately to: d x @ r t 2 ? r t + 260 ( 10 ) and the output switching frequency will be halved with respect to the oscillator one because an in- ternal t flip-flop (see block diagram, fig. 1) is acti- vated. fig. 29 shows the operation. the half duty cycle option speeds up the dis- charge of the timing capacitor c t (in order to get duty cycles as close as possible to 50%) so the oscillator frequency - with the same r t and c t - will be slightly higher. the halving of frequency can be used to reduce losses at light load in all those systems that must comply with requirements regarding energy con- sumption (e.g. monitor displays). + - c d97in502 dis d r q disable uvlo 2.5v 14 disable signal figure 28. disable (latched) l4990 - l4990a 13/24
demonstration board to evaluate the device performance, a demon- stration board has been realized. despite its sim- plicity, it exploits most of the features of the l4990. the board embodies an application based on the following specification of universal mains ac-dc adapter: input voltage range: 85-270 vac (50/60 hz) output voltage: 15 v output current: 0.5 to 2a output voltage ripple : 300 mv (max.) load regulation: 5% (0.5 to 2 a load change) target efficiency @ iout = 2 a: ; 80% over the input voltage full range some preliminary decisions, concerning topology, operating mode, switching frequency, maximum duty cycle allowed and control technique, have been made. as for topology, at this power level and output voltage, flyback is the most advantageous one, mainly because of its simplicity, which means low parts count, low cost and inherent high efficiency. a peculiar design choice aiming at optimizing the overall system concerns the operating mode: the converter will work in continuous current mode at low input voltages, when input current is greater, and in discontinuous mode at higher input volt- ages. numerous benefits originate from that. compared to discontinuous current mode, con- tinuous operation involves lower peak currents (typ. -40%) at the same throughput power. this implies less stress for all power components. the transformer inductance is higher and, there- fore, a smaller air gap is required for a given core: this increases primary-to-secondary coupling and, as a consequence, reduces leakage inductance and improves energy transfer. both efficiency and load regulation will take advantage of that. another point in favor is a reduction of the mini- mum output power that the system is able to de- liver keeping the output well regulated. few components are required in addition for slope compensation. actually, continuous mode flyback suffers also from a poor dynamic behavior during load tran- sients because of the narrow bandwidth of the control loop due to stability problems. however, great dynamic performance is not required to ac- dc adapters, so this problem is of no concern. the boundary between the two operating modes has been set at about 150 vac (@ iout=2a). the selection of the switching frequency is a mat- ter of trade-off between achieving a small trans- former size and high efficiency. 200 khz seems to be a good compromise. in this application, the wide input voltage range requires a large duty cycle sweep. the higher is the maximum duty cycle, the larger is the operat- v15=gnd v5=v13=gnd v15=vref v5=v13=gnd t d t d t c t c v2 v10 v2 v10 d x = t c t c +t d d x = t c 2t c +t d d97in498 figure 29. half duty cycle option. l4990 - l4990a 14/24
ing conditions range, in terms of input voltage and output current, that the converter is able to cover but, on the other hand, the higher is the peak cur- rent on the secondary side. as to this point, the l4990 turns out to be particu- larly useful since it allows to set any maximum duty cycle greater (and lower) than 50% with very good precision. in the present case, a maximum duty cycle of 60% for steady state operation has been selected and an extra 5% is allowed to take transients into account. since it is not requested a very tight tolerance on the output, the feedback employs a primary side voltage sensing technique to reduce cost and complexity of the circuit. the same technique has been used to protect against output overvoltages. the electric schematic is shown in fig. 30. the pcb layout is shown in figg. 31 and 32. table 1 and 2 summarize typical system performance, while table 3 lists the relevant bill of material, where details are given only for critical compo- nents and/or where useful. warning: the ntc for inrush current limitation is not assembled, thus use caution when connecting the demo board to the mains directly. the use of a variac or an isolation transformer is recom- mended. table 1. system efficiency. i out =1a i out =2a v in (vac) v out (v) effic. % v ou t (v) effic. % 85 14.93 83.7 14.53 84.3 110 14.95 82.5 14.55 84.9 220 14.95 81.4 14.57 85.2 270 14.96 76 14.59 81.6 table 2. system performance. line regulation v in = 85 to 270 vac i out = 0.5a 30mv load regulation i out = 0.5a to 2a v in = 85 vac v in = 270 vac 0.95v 0.90v maximum effic. v in = 190 vac i out =2a 86.2% output ripple v in = 85 to 270 vac i out =2a < 200mv minimum load v in = 270 vac v out < 20v 150ma transition volt. from c.c.m to d.c.m i out =2a 160v 85 to 270 vac b1 c1 r12 r19 c8 ntc 10 r7 13 r24 15 12 r11 8 14 6 r6 r15 r2 4 3 2 r9 c4 r10 7 r23 q1 r16 c12 d3 d4 c2 r17 gnd d97in499b l4990 r13 r1 c10 c13 d2 r14 r5 c3 r3 c7 r4 59 dcc r8 vref c5 c6 q2 rct ss r22 c15 dc-lim sgnd c14 r20 r21 c11 11 pgnd isen out vc vcc dis comp vfb t1 15v/2a d1 figure 30. ac-dc adaptor electric schematic l4990 - l4990a 15/24
table 3. components list of the fig. 30 ac-dc adaptor electric schematic. component reference value description resistors r1 1.6k w 2%, 1/8w r2 9.1k w 2%, 1/8w r3, r14 10 w 5%, 1/8w r4 360k w 2%, 1/8w r5 27k w 2%, 1/8w r6 200k w 2%, 1/8w r7 4.7 w 2%, 1/8w r8, r9 4.7k w 2%, 1/8w r10 5.6k w 2%, 1/8w r11 1 w 2%, 1/2w, metallic film (low inductance) r12, r13 24k w 2%, 1/2w r15 330 w 5%, 1/8w r16 - not used r17 390 w 5%,1w, 2 paralleled resistors (not used) r19 100k w 5%, 1w r20, r21 470k w 2%, 1/8w r22 200 w 5%, 1/8w r23 2k w 2%, 1/8w r24 1k w 5%, 1/8w capacitors c1 100 m f 400v, ncc-smh or equiv. c2 330 m f 25v, ncc-lxf or equiv., 3 paralleled capacitors c3 47 m f 25v, electrolytic c4 1 m f 10v, electrolytic c5 1nf j precision c6, c15 10nf c7, c14 330pf c8 330pf 160v, polypropilene c9 100nf c10 220nf c11 100pf ceramic c12 - not used c13 4.7nf 630v transformer t1 380 m h core: efd25, philips, 3f3 ferrite (or equivalent) primary: 46 t, litz wire 20 x 0.1, interleaved assembly secondary: 6 t, 4 paralleled litz wire 20 x 0.1 auxiliary: 7 t (evenly spaced), ? 0.2 mm gap ~ 0.7mm transistors q1 stp5na80 st, to220 package q2 2n2222 st (or equivalent) diodes b1 df04m gi (or equivalent) d1 stps20100ct st, shottky, to220 package d2, d3 1n4148 st (or equivalent) d4 byt11-600 st, f126 package fuse fuse t2a250v elu (or equivalent) ntc ntc - not used (see warning) l4990 - l4990a 16/24
figure 31. ac-dc adaptor pcb layout (1.25 :1 scale) - component side. figure 32. ac-dc adaptor pcb layout (1.25 :1 scale) - back side. l4990 - l4990a 17/24
layout hints. generally speaking a proper cir- cuitboard layout is vital for correct operation but is not an easy task. careful component placing, cor- rect traces routing, appropriate traces widths and, in case of high voltages, compliance with isolation distances are the major issues. the l4990 eases this task by putting two pins at disposal for sepa- rate current returns of bias (sgnd) and switch drive currents (pgnd) the matter is complex and only few important points will be here reminded. 1) all current returns (signal ground, power ground, shielding, etc.) should be routed sepa- rately and should be connected only at a single ground point. 2) noise coupling can be reduced by minimizing the area circumscribed by current loops. this applies particularly to loops where high pulsed currents flow. 3) for high current paths, the traces should be doubled on the other side of the pcb whenever possible: this will reduce both the resistance and the inductance of the wiring. 4) magnetic field radiation (and stray inductance) can be reduced by keeping all traces carrying switched currents as short as possible. 5) in general, traces carrying signal currents should run far from traces carrying pulsed cur- rents or with quickly swinging voltages. from this viewpoint, particular care should be taken of the high impedance points (current sense in- put, feedback input, ...). it could be a good idea to route signal traces on one pcb side and power traces on the other side. 6) provide adequate filtering of some crucial points of the circuit, such as voltage refer- ences, ic's supply pins, etc. application ideas here follows a series of ideas/suggestionsaimed at either improving performance or solving common application problems of l4990-basedsupplies. d97in504 l4990 pgnd isen out v c sgnd v in isolation boundary 10 9 13 11 12 figure 33. isolated mosfet drive & current transformer sensing in 2-switch topologies. l4990 v ref t std1nb50-1 v cc v in 22v d97in505a 2.2m w 33k w self-supply winding 8 4 12 11 47k w figure 34. low consumption start-up l4990 - l4990a 18/24
d97in506 l4990 pgnd isen out v c v in 9 10 13 11 8 v cc figure 35. bipolar transistor drive d97in507 + - ea r i + 1.3ma r d r 2r 12 c f r f 6 5 from v o 2.5v + - ea r p + 1.3ma r d r 2r 12 c f r f 6 5 from v o 2.5v error amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current. c p r i error amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current. vfb vfb comp comp sgnd sgnd figure 36. typical e/a compensation networks. l4990 - l4990a 19/24
l4990 comp d97in508 tl431 v out vfb 6 5 figure 37. feedback with optocoupler l4990 optional d97in509a i v ref sgnd r t c t rct r slope r sense isen l4990 optional i v ref sgnd r t c t rct r slope r sense isen l4990 optional out sgnd r r r slope r sense isen c slope 4 2 13 12 4 2 13 12 13 12 10 figure 38. slope compensation techniques figure 39. protection against overvoltage/feedbackdisconnection (latched) l4990 d97in510 sgnd dis v cc r start pgnd 8 14 12 11 l4990 d98in904 sgnd dis v cc r start pgnd 8 14 12 11 v z 2.2k l4990 - l4990a 20/24
l4990 d97in511a dc v cc vref r start 3 12 8 4 11 figure 40. protection against overvol- tage/feedback disconnection (not latched) d97in512a pgnd l4990 optional vref sgnd dis isen i 4 14 13 12 11 r sense r 2 r 1 i pk i pk max @ 2.5 r sense 1- r 2 r 1 ? figure 41. device shutdown on overcurrent d97in513 pgnd l4990 out sgnd isen l p r ff r v in r ff = 510 6 rl p r sense r sense 13 10 12 11 80 400v dc figure 42. constant power in pulse-by-pulse current limitation (flyback discontinuous) references [1] efficient active clamp for off-line applications using l4990 and l6380 (n.tricomi, g. gattavari, c. adragna, pcim96 - nurberg). [2] 25w off-line autoranging battery charger with l4990 (an889) [3] 300w secondary controlled two-switch forward converter with l4990 (an890) [4] smps with l4990 for multisync monitors (an891) [5] high performance vrm using l4990a, for pentium pro ? processor (an908). l4990 dc 10k comp 3 6 12 13 sgnd isen d97in570a figure 43. voltage mode operation. l4990 - l4990a 21/24
dip16 dim. mm inch min. typ. max. min. typ. max. a1 0.51 0.020 b 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 0.050 outline and mechanical data l4990 - l4990a 22/24
dim. mm inch min. typ. max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.1 0.3 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 10.1 10.5 0.398 0.413 e 7.4 7.6 0.291 0.299 e 1.27 0.050 h 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.4 1.27 0.016 0.050 k0 (min.)8 (max.) hx 45 a e b d e a1 h l c k 16 1 8 9 so16 wide outline and mechanical data l4990 - l4990a 23/24
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com l4990 - l4990a 24/24

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